Electrical and Electronics

Cryptography circuits for portable electronic devices provide user authentication and secure data communication. These circuits should, in general, occupy small chip area, consume low power, handle several cryptography algorithms, and provide acceptable performance. This paper presents the simulation and synthesis of three standard cryptography algorithms on a universal architecture. The cryptography processor implements both private key and public key algorithms and meets the power and performance specifications. The mentor graphics modelsim tool is used for design and simulation and also Synopsys Design Compiler tool is used for synthesis. TSMC 65nm library is used for the synthesis.

In this paper experimentally investigated error-free underwater wireless optical communication (UWOC) system over 7m path in laboratory tap water with up to 46.808dB and BER less than 2.487×10-6. The laser diode source of wavelength 532 nm with 50mW has modulated by intensity modulation/direct detection (IM/DD) technique, BER and S/N have inspected in an underwater optical wireless communication channel with five different water channels types. These are tap water, different concentration of Maalox (Mg(OH)2 and Al(OH)3) in order to obtain high turbid water and salt with Maalox. The analysis of BER has achieved for pulse width modulation (PWM) to transmit a text from optical transmitter to receiver. Results shows that salt and Maalox content decreases the received power, S/N and increase in BER. Also, that 532nm wavelength is the suitable choice for a clear water channel.

We study jitter control in networks with guaranteed quality of service (QoS) from the competitive analysis (as mentioned in [1]) point of view. we analyze on-line algorithms for single jitter regulator that control jitter and compare their performance to the best possible by an off-line algorithm as proposed in [1]. For delay jitter, where the goal is to minimize the difference between delay times of different packets, we show that a simple on-line algorithm using a buffer of B slots guarantees the same delay jitter as the best off-line algorithm using buffer space B/2. We prove that the guarantees made by our (proposed in [1]) on-line algorithm hold, even for simple distributed implementations, where the total buffer space is distributed along the path of the connection, provided that the input stream satisfies a certain simple property. The significance of the results is that it proves the on-line algorithm to be the best possible algorithm to reduce delay jitter for a given buffer size B. The main argue is even if both the distributed and non distributed algorithms get same jitter which one has more advantage. We focused on the advantages of distributing the buffers. The algorithm in its original form is applicable only to a fixed number of packets. We extend the results to a more practical model in which we compare off-line algorithm with n inputs and on-line algorithms with n1 (>n) inputs.

One of the major problems in power system is the occurrence of disturbances that affect the quality of electricity supply. Fault location detection is therefore the key to reliable operation of power equipments and satisfactory service delivery with minimum interruption. This need has given rise to fault location techniques so that the effects of fault can be mitigated with appropriate corrective measures. This paper, thus, presents two algorithmic approaches towards fault location detection with and without using transmission line parameters. A comparison between these techniques, that is the impedance-based method and travelling wave-based method was done to ascertain their degree of efficacy in estimating the distance of various faults at different locations on the transmission line model. The modelling and simulations were done using Simulink and the algorithms of both methods were written using MATLAB codes. Lower the value of percentage error, better the accuracy of algorithm.

The wide range of transmission medium is covered by the wireless sensor network. Due to its increasing popularity many research are done to increase its energy level for effective transmission. The earliest approach in transferring packets with prior processing is more efficient which used the concept of Ant Colony Optimisation approach to obtain the chain.  This existing Power Energy Gathering with Ant colony approach (PEG-ACO) is efficient in minimising transmission distance but there is no mechanism to find out interrupts in transmission, packet loss due to node failure. This paper proposes routing algorithm artificial bee colony approach which optimises the energy level in nodes. The chain is obtained by clustering the nodes with multiple mobile sinks using Artificial Bee Colony (PEG-ABC) concept in order to avoid node failure and packet lost. The load among the nodes is balanced for effective transmission of packets with less energy consumption.

To exploit limited spectrum efficiently CR technology allows unlicensed users to access licensed spectrum bands. Since licensed users have priorities to use the bands, the unlicensed users need to continuously monitor the licensed user’s activities to avoid interference and collisions. To obtain reliable results of the licensed user’s activities is the main task for spectrum sensing. Based on the sensing results the unlicensed users should adapt their transmit powers and access strategies to protect the licensed communications. This paper presents a new spectrum sensing method based on Time-Frequency Analysis. Several realistic signals are taken under different noisy conditions for analysis using Frequency Slice Wavelet Transform (FSWT) to verify its superiority in spectrum sensing.

In this paper, we have presented a wide range phase locked loop (PLL) based frequency synthesizer using a voltage tuning variable length ring oscillator (RO). The frequency of the used ring oscillator can be changed dynamically from one frequency to another frequency by changing the length of the oscillator electronically. An analog frequency tuning mechanism is also introduced here to make it suitable for applications in PLL based systems. The proposed PLL based frequency synthesizer can successfully synthesize different harmonics (Nf_r ) of the reference signal (f_r ) within the lock range of the oscillator. The experimental results from a prototype hardware electronic circuit are presented here to support the validity of the proposed architecture of the RO and the frequency synthesizer.

A linear adaptive beamforming structure consists of an antenna array and a digital signal processor to adjust adaptively its weight according to the particular criterion and adaptive algorithm. There are many criteria and adaptive algorithms to minimum co-channel interference (or multi-access interference).Different Algorithms (S.Strergiopoulos, 2001& Joseph C. Liberti, et al, 1999) are employed to determine the complex weights of the signal and to produce narrow beams toward intended users and deep nulls in the direction of interference.

Network-on-Chip (NoC) paradigm allows designers to integrate efficiently more intellectual properties (IPs) into a single chip system. However, the power consumption has become one of the most critical issues for designing such large complex systems. Low power design can be achieved by scaling the voltage and frequency of the target components. The question is how to make the voltage-frequency scaling adaptable to the required performance of the system at run-time while reducing as much as possible the power consumption. This paper presents a novel solution for NoC architectures to reduce power consumption. As the communication traffic is not equally distributed over the network architecture, depending on the communication load, each router in the network will be applied with a corresponding voltage and frequency to minimize the power consumption while keeping necessary communication throughput.

A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source - Coupled Logic (SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power consumption and the operating frequency. The multiplexer design employs CMOS transistors as transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at a supply voltage of 400 mV with a bias current ranging in the order of few pA. The ON and OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 0.79 µW for a dynamic range of 1µV to 0.4 V.